The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor devices require design features below about 0.18 .mu.m, e.g., about 0.15 .mu.m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 .mu.m and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so called "short-channel" effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the, gate can cause gate oxide charging and threshold voltage and thus reduce instabilities. Shallow junction, lightly- or moderately-doped source drain extension-type transistor structures have been developed.
For p-channel MOS transistors, the major "short-channel" effects which limits performance arise from "punch-through" effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned "punch-through" current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS-type transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS- and CMOS-type devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped source/drain regions are laterally displaced away from the gate by use of a pair of spacers on opposite sidewalls of the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
However, in the case of MOS and CMOS devices, formation of junctions having desired characteristics (e.g., the spatial relationship between the impurity concentration peak and the lightly- or moderately-doped source/drain region) is problematic.
Thus a need exists for improved semiconductor manufacturing methodology for fabricating MOS and CMOS transistors which does not suffer from the above-described drawback associated with achieving a desired spatial relationship between the impurity concentration peak and the lightly- or moderately-doped source/drain region. Moreover, there exists a need for an improved process for fabricating transistor-based devices which permits capacitance between the lightly- or moderately-doped source/drain region and the semiconductor substrate to be modulated, which process is fully compatible with conventional process flow and provides increased manufacturing throughput and product yield.
The present invention fully addresses and solves the above-described drawback attendant upon conventional processing for forming submicron-dimensioned transistors for use in high-density integrated semiconductor devices, particularly in providing a process for forming a semiconductor device comprising a retrograde impurity profile having an impurity concentration peak wherein the distance between the depth of the peak and the lightly- or moderately-doped source/drain region can be precisely determined, thereby permitting modulation of the capacitance between the lightly- or moderately-doped source/drain region and the semiconductor substrate.